MT18HTS25672RHZ-80EH1 Micron Technology Inc, MT18HTS25672RHZ-80EH1 Datasheet - Page 10

• Manufacturer Part Number: MT18HTS25672RHZ-80EH1
• Description: MODULE DDR2 SDRAM 2GB 200SORDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTS25672RHZ-80EH1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 800MT/s
• Features: -
• Package / Case: 200-SORDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IDD Specifications
Table 8: DDR2 I
Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256
Meg x 8) component data sheet
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
= CL (I
t
are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
RCD (I
RP (I
OUT
RP =
DD
DD
),
); CKE is LOW; Other control and address bus inputs are stable;
= 0mA; BL = 4, CL = CL (I
DD
t
t
RAS =
DD
RP (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DD
t
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
t
RP (I
DD
t
CK =
Specifications and Conditions – 2GB
DD
DD
DD
t
t
); CKE is HIGH, S# is HIGH between valid commands;
CK (I
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
CK (I
), AL = 0;
),
t
RC =
DD
t
CK =
); REFRESH command at every
t
DD4W
RC (I
t
CK =
t
CK (I
DD
t
),
DD
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
CK (I
t
),
RAS =
t
CK =
t
t
RAS =
CK =
DD
t
CK =
),
t
t
CK =
t
t
RAS MIN (I
CK (I
RAS =
t
CK (I
t
OUT
t
CK =
t
RAS MAX (I
t
CK (I
CK =
10
t
DD
CK
= 0mA; BL = 4, CL
DD
t
),
t
DD
RAS MAX (I
CK (I
),
t
t
CK (I
); CKE is HIGH,
RAS =
t
DD
RC =
t
RFC (I
DD
Fast PDN
exit
MR[12] = 0
Slow PDN
exit
MR[12] = 1
),
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
RCD =
t
t
),
); CKE is
RC
RAS
DD
t
RP =
DD
)
),
Combined
Symbol
I
I
I
I
I
I
I
CDD4W
I
I
CDD2Q
CDD2N
CDD3N
I
I
CDD2P
CDD3P
CDD4R
CDD0
CDD1
CDD5
CDD6
© 2010 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E
1098
1548
1548
2223
918
126
513
558
333
153
648
126
1008
1323
1323
2043
-667
873
126
423
468
333
153
603
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA