MCZ33989EG Freescale Semiconductor, MCZ33989EG Datasheet - Page 34

• Manufacturer Part Number: MCZ33989EG
• Description: IC SYSTEM BASIS CHIP CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33989EG

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 28-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20. IOR Status Bits
Wake-up Input Register (WUR)
in both Normal and Standby modes as port expander, as well
Table 21. WUR Register
Table 22. WUR Control Bits
Table 23
Table 23. WUR Status Bits
34
33989
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Notes: Status bits have two functions. After SBC wake-up, they indicate the wake-up source (Example: L2WU set at 1 if wake-up source is L2
input). After SBC wake and once the WUR has been read, status bits indicates the real time state of the LX inputs (1 mean LX is above
threshold, 0 means that LX input is below threshold).
only if SBC was in Stop mode.
The local wake-up inputs, L0, L1, L2, and L3 can be used
LCTR3
Reset Condition
If, after a wake-up from LX input, a WD timeout occurs before the first reading of the WUR register, the LXxWU bits are reset. This can occur
Reset Value
x
x
x
x
0
0
1
1
VSUPLOW
Status Bit
$100B
Status Bit
WUR
V2LOW
DEBUG
provides Status bits data.
HS1OT
L3WU
L2WU
L1WU
L0WU
LCTR2
x
x
x
x
0
1
0
1
W
R
V2 Below 4.0 V
High Side 1 Over Temperature
V
If Set, SBC Accepts Command to go to Debug Modes (No WD)
Wake-up Occurred (Sleep/Stop Modes), Logic State on Lx (Standby/Normal Modes)
SUP
LCTR1
Below 6.1 V
0
0
1
1
x
x
x
x
LCTR3
L3WU
D3
0
LCTR0
0
1
0
1
x
x
x
x
POR, NR2R, N2R, STB2R, STO2R
LCTR2
L2WU
High Level Sensitive
Both Level Sensitive
as and for waking up the SBC in Sleep or Stop modes.
Please see
L0 and L1 are configured together. Bits L2 and L3 are
configured together. Please see
Low Level Sensitive
D2
0
Inputs Disabled
The wake-up inputs can be configured separately, while
L0/L1 Config
Description
Description
—
Table
21.
LCTR1
L1WU
Analog Integrated Circuit Device Data
D1
0
Table
High Level Sensitive
Both Level Sensitive
Low Level Sensitive
Freescale Semiconductor
Inputs Disabled
L2/L3 Config
22.
—
LCTR0
L0WU
D0
0