MCZ33989EG Freescale Semiconductor, MCZ33989EG Datasheet - Page 22

• Manufacturer Part Number: MCZ33989EG
• Description: IC SYSTEM BASIS CHIP CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33989EG

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 28-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the MCU to enter its low power mode, a deglitcher time of
typical 40 µs is implemented.
SOFTWARE WATCHDOG (SELECTABLE WINDOW
OR TIMEOUT WATCHDOG)
modes is to monitor MCU. The Watchdog can be either
window or timeout. This is selectable by SPI (register TIM1,
bit WDW). Default is window watchdog. The period for the
watchdog is selectable from the SPI from 10 ms to 350 ms
(register TIM1, bits WDT0 and WDT1). When the window
watchdog is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. Refer to the SPI TIM register description.
Watchdog can only be cleared within the open window time.
An attempt to clear the watchdog in the closed window will
generate a reset. Watchdog is cleared through SPI by
addressing the TIM1 register.
Table 5. Reset and Watchdog Output Operation
Watchdog timeout. Please refer to
to 5.0 V because of its internal limited current drive capability.
22
33989
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
Notes
Devices Power-up
V
V
Watchdog Timeout Reached
V
V
Watchdog Timeout Reached
27.
Software watchdog uses in the SBC Normal and Standby
In Mode 2, the reset pin is not activated in case of
For debug purposes at 25°C, the Reset pin can be shorted
DD1
DD1
DD1
DD1
Normal Watchdog Properly Triggered
Normal Watchdog Properly Triggered
< RST
< RST
WD stays low until the Watchdog register is properly addressed through SPI.
SPI Stop/ Sleep Command
TH
TH
SPI CS
Events
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
SBC in Normal or Stand-by mode
Table 6
Figure 9. Operation Entering Stop Mode
for more detail.
1 or 2 (Safe Mode)
2 (Safe Mode)
2 (Safe Mode)
2 (Safe Mode)
Mode
1
1
1
t
CS
STOP
RESET PIN DESCRIPTION
microcontroller. Modes 1 and 2 are available for the reset pin
(please refer to
• V
• Power-on reset — At device power-on or at device wake-
will pull the reset pin low for the duration of the reset time
(parameter RST
RESET AND WATCHDOG OPERATION: MODES1
AND 2
operation:
Figure 9
A reset output is necessary and available to reset the
Reset causes when SBC is in mode 1:
threshold (parameter R
V
up from Sleep mode, the reset is maintained low until V
is within its operation range.
Watchdog timeout — If watchdog is not cleared, the SBC
Watchdog and Reset functions have two modes of
DD1
DD1
no I
SBC in Stop mode
DD1
falling out of range — If V
returns to the normal voltage.
I
indicates the operation to enter Stop mode.
DD1DGLT
over I wake-up
Table 5
DUR)
.
WD Output
Low to High
Low (Note)
Low (Note)
Analog Integrated Circuit Device Data
for reset pin operation).
High
High
High
High
STTH
), the ret pin is pulled low until
SBC in Stop mode
with I
DD1
Freescale Semiconductor
DD1
falls below the reset
over I wake-up
Reset Output
Low to High
High
High
High
Low
Low
Low
DD1