DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 53

• Manufacturer Part Number: DS33Z11+
• Description: IC MAPPER ETHERNET 169-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11+

• Applications: Data Transport
• Interface: SPI/Parallel
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 169-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.15.4.1 Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit
error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream
is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
8.15.4.2 Performance Monitoring Update
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the performance monitoring update signal (PMU). During the counter register update process, the
performance monitoring status signal (PMS) is de-asserted. The counter register update process consists of
loading the counter register with the current count, resetting the counter, forcing the zero count status indication
low for one clock cycle, and then asserting PMS. No events shall be missed during an update procedure.
8.16 Transmit Packet Processor
The Transmit Packet Processor accepts data from the Transmit FIFO, performs bit reordering, FCS processing,
packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The
data output from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream (bit
synchronous mode). HDLC processing can be disabled (clear channel enable). Disabling HDLC processing
disables FCS processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame
padding. Only bit reordering and packet scrambling are not disabled.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output from the Transmit FIFO with the MSB in
TFD[7] (or 15, 23, or 31) and the LSB in TFD[0] (or 8, 16, or 24) of the transmit FIFO data TFD[7:0] 15:8, 23:16,
or 31:24). If bit reordering is enabled, the outgoing 8-bit data stream DT[1:8] is output from the Transmit FIFO with
the MSB in TFD[0] and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. In bit synchronous mode, DT [1] is
the first bit transmitted. Bit Reordering can be controlled by address pin A0 in Hardware Mode.
FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 or CRC-32
calculation over the entire packet. The polynomial used for FCS-16 is x
FCS-32 is x
calculation. The FCS type is programmable. If FCS append is enabled, the calculated FCS is appended to the
packet. If FCS append is disabled, the packet is transmitted without an FCS. The FCS append mode is
programmable. If packet processing is disabled, FCS processing is not performed.
Packet error insertion inserts errors into the FCS bytes. A single FCS bit is corrupted in each errored packet. The
FCS bit corrupted is changed from errored packet to errored packet. Error insertion can be controlled by a
register or by the manual error insertion input (LI.TMEI.TMEI). The error insertion initiation type (register or input)
is programmable. If a register controls error insertion, the number and frequency of the errors are programmable.
If FCS append is disabled, packet error insertion will not be performed. If packet processing is disabled, packet
error insertion is not performed.
Stuffing inserts control data into the packet to prevent packet data from mimicking flags. A packet start indication
is received, and stuffing is performed until, a packet end indication is received. Bit stuffing consists of inserting a
'0' directly following any five contiguous '1's. If packet processing is disabled, stuffing is not performed.
There is at least one flag plus a programmable number of additional flags between packets. The inter-frame fill
can be flags or all '1's followed by a start flag. If the inter-frame fill is all '1's, the number of '1's between the end
and start flags does not need to be an integer number of bytes, however, there must be at least 15 consecutive
'1's between the end and start flags. The inter-frame padding type is programmable. If packet processing is
disabled, inter-frame padding is not performed.
Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a
packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. The abort
sequence is FFh. If packet processing is disabled, packet abort insertion is not performed.
The packet scrambler is a x
runs continuously, and is never reset. In bit synchronous mode, scrambling is performed one bit at a time. In byte
32
+ x
26
+ x
23
+ x
43
22
+ 1 scrambler that scrambles the entire packet data stream. The packet scrambler
+ x
16
+ x
12
+ x
11
+ x
10
53 of 172
+ x
8
+ x
7
+ x
5
+ x
16
4
+ x
+ x
2
12
+ x + 1. The FCS is inverted after
+ x
5
+ 1. The polynomial used for