DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 49

• Manufacturer Part Number: DS33Z11+
• Description: IC MAPPER ETHERNET 169-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11+

• Applications: Data Transport
• Interface: SPI/Parallel
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 169-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.14.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown
SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data
Register. These indirect registers are accessed through the MAC Control Registers defined in
MDC clock is internally generated and runs at 1.67 MHz.
Figure 8-8 MII Management Frame
READ
WRITE
Preamble
111...111
111...111
Figure
32 bits
8-8. The read/write control of the MII Management is accomplished through the indirect
2 bits
Start
01
01
Opco
2 bits
de
10
01
Phy Adrs
PHYA[4:0]
PHYA[4:0]
5 bits
49 of 172
PHYR[4:0]
PHYR[4:0]
Phy Reg
5 bits
Aroun
2 bits
Turn
ZZ
10
d
ZZZZZZZZZ
PHYD[15:0]
bits
Data
16
Idle
Bit
1
Z
Z
Table
8-6. The