DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 145

• Manufacturer Part Number: DS33Z11+
• Description: IC MAPPER ETHERNET 169-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11+

• Applications: Data Transport
• Interface: SPI/Parallel
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 169-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The
data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss.
Figure 10-9 RMII Receive Interface Functional Timing
10.3 SPI Interface Mode and EEPROM Program Sequence
The DS33Z11 will act as an SPI Master when configured with MODEC[1:0] to read the configuration from an
external Serial EEPROM, such as the Atmel AT25160A. The EEPROM must be programmed with the data
structure shown in
falling edge of SPICK. The MISO data can be sampled on rising or falling edge of SPICK based on the CKPHA
pin input. The SPICK is generated by the DS33Z11 at a frequency of 8.33 MHz, derived from an external
SYSCLKI of 100 MHz. The initialization sequence is commenced immediately after power up reset or a rising
edge of the RST input pin. The SPI master initiates a read with the instruction code 0000x011b; followed by the
address location. The SPI_CS is held low until the data addressed is read and latched. The DS33Z11 begins
reading the EEPROM at address 0000h. Data is sequentially latched until the last data byte is read and latched.
The indirect MAC registers require a special program sequence at the end of the EEPROM file. Four MAC
registers can be programmed in the EEPROM Mode: SU.MACCR, SU.MACMIIA, SU.MACMIID, and
SU.MACFCR. All other indirect MAC registers do not need to be initialized for EEPROM mode operation. The
indirect MAC registers are programmed using four separate seven-byte records from the EEPROM. An example
is shown in
Figure 10-10 SPI Master Functional Timing
CRS_DV
REF_CLK
RXD[1:0]
SPI_CS*
CKPHA=1
MOSI
MISO
CKPHA=0
SPICK
SPICK
Table
P
R
0
10-2.
0
Table
E
1
0
0
A
0
0
2
10-1. The MOSI (Master Out Slave In) signal can be selectively output on the rising or
M
0
0
3
B
X
4
L
5
0
E
6
1
7
1
8
0
145 of 172
9
0
10
0
11
0
20
0
21
0
22
0
23
0
24
7
25
6
5
26
4
27
3
28
F
2
29
C
1
30
S
0
31