DS33Z11+ Maxim Integrated Products, DS33Z11+ Datasheet - Page 30

• Manufacturer Part Number: DS33Z11+
• Description: IC MAPPER ETHERNET 169-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11+

• Applications: Data Transport
• Interface: SPI/Parallel
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 169-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.1 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC[1:0] =
00 and HWMODE pin = 0 the read-write strobe mode is enabled and a negative pulse on RD performs a read
cycle, and a negative pulse on WR performs a write cycle. When MODEC[1:0] pins = 01 and HWMODE pin = 0
the data strobe mode is enabled and a negative pulse on DS when RW is high performs a read cycle, and a
negative pulse on DS when RW is low performs a write cycle. The read-write strobe mode is commonly called the
“Intel” mode, and the data strobe mode is commonly called the “Motorola” mode.
8.1.2
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3
The interrupt (INT) pin is configurable to drive high or float when not active. The INTM bit controls the pin
configuration, when it is set the INT pin will drive high when not active. After reset, the INT pin is in high-
impedance mode until an interrupt source is active and enabled to drive the interrupt pin.
8.2 SPI Serial EEPROM Interface
The SPI interface is a 4 signal serial interface that allows connection to a serial EEPROM for initialization
information. The DS33Z11 will act as an SPI Master when configured with MODEC[1:0] to read from an external
Serial EEPROM. The reading sequence is commenced upon initial reset or rising edge of the RST input pin. The
CKPHA pin controls the sampling and update edges of the MISO and MOSI signals. The MISO data can be
sampled on rising or falling edge of SPICK. The MOSI (Master Out Slave In) can be selectively output on the
rising or falling edge of SPICK. The SPICK is generated by the DS33Z11 at a frequency of 8.33 MHz. This
frequency is derived from an external SYSCLKI (100 MHz). The instruction to initiate a read is 0000x011; this is
followed by the address location 0. The SPI_CS is low till the data addressed
The DS33Z11 will provide the starting address (0000000) and the data is sequentially latched till the last data is
read and latched. The MAC specific registers, which are addressed indirectly, are written at the end of the normal
control registers. More details of the programming sequence an functional timing information can be found in
Section 10.3. The indirect registers related to the MAC are programmed using a special command format as
shown in
Clear on Read
Interrupt and Pin Modes
Table
10-2.
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(Table
10-1) is read and latched.