PI7C9X20404GPBNBE Pericom Semiconductor, PI7C9X20404GPBNBE Datasheet - Page 3

• Manufacturer Part Number: PI7C9X20404GPBNBE
• Description: IC PCIE PACKET SWITCH 148LFBGA
• Manufacturer: Pericom Semiconductor
• Series: GreenPacket™r

Specifications of PI7C9X20404GPBNBE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 148-LFBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

REVISION HISTORY
Date
12/13/06
1/3/06
5/22/07
7/11/07
8/29/07
10/04/07
1/11/08
June 2009 – Revision 1.6
Pericom Semiconductor
Revision Number
0.1
0.4
0.5
0.6
0.7
0.8
1.0
Proofreading an Editing
Revision of the registers and the description. Packaging mechanical
Removed Reference Clock Output related info from 1. Features
Updated Chapter 3.5 JTAG Signals description
Modified Chapter 3.4 MISCELLANEOUS SIGNALS
Description
Initial Preliminary Datasheet
added
Corrected pin description for ATT_IND[4], TEST3, TEST4, TEST5
and TEST 6 in section 3 and 4
Corrected register description for offset F0h in section 7.2.70
(advanced power saving), 3 Pin Description (RREF_CO, REFCLK,
VDDIO), 4. Pin Assignment (RREF_CO to TEST7, REFCLK to
NC, VDDIO to VDDR), 8 Clock Scheme (description), 12.2 AC
Specification (VDDIO)
Updated “ORDERING INFORMATION”
Added 12.3 AC Specifications: Transmitter and Receiver
Specifications
Updated 8 Clock Scheme (Table 8-1)
Updated Chapter 14 Ordering Information (PI7C9X20404GPNBE)
Updated Pericom Logo
Added Disclaimer
Added Chapter 6.2 SMBus
Added SMBus related items in Chapter 1 Features
Modified SMBus related pins (GPIO[5:7])
Corrected Chapter 6. EEPROM and Chapter 7. Register Description
Corrected Chapter 3. Pin Description (PORTACT, TEST) and
Chapter 4. Pin Assignment (B9, D3, D12, D14, E12, E14, G12, G14,
H12, H14, K12, K14, L12, L13, L14, N12, N14, P2, P12, P14)
Corrected Chapter 3.6 Power Pins (VDDC, VDDA, VDDCAUX to
1.1V), Chapter 3.4 Misc. Signals (TEST6 corrected, TEST7 to
PWR_SAV)
Updated Chapter 7.2.53 bit [15:0]
Updated Chapter 7.2.53
Remove VDDP, VDDAUX from Chapter 11 Power Management
and Chapter 12.1 Absolute Maximum Ratings
Revised Chapter 11 Power Management
Updated Chapter 3 Pin Description (PERP/PERN and PETP/PETN’s
description, WAKEUP_L’s description, VC1_EN’s name and
description, SLOT_IMP’s description, HOTPLUG’s description,
SLOTCLK’s description, PWR_IND’s description, ATT_IND’s
description, MRL_PDC’s description, PWR_ENA_L’s description,
EEPD’s description, SMBDATA’s description, SCAN_EN’s
description, PORTERR’s name and description)
Updated Chapter 4 Pin Assignment (VC_RS to VC1_EN,
PORTACT to PORTERR)
Updated 5.1 Physical Layer Circuit and Chapter 5.6 Queue
Updated Disclaimer and Footer
Updated Chapter 14 Ordering Information
Fixed Chapter 6.1.4 Mapping EEPROM format
Page 3 of 79
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