PI7C9X20404GPBNBE Pericom Semiconductor, PI7C9X20404GPBNBE Datasheet - Page 24
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PI7C9X20404GPBNBE
Manufacturer Part Number
PI7C9X20404GPBNBE
Description
IC PCIE PACKET SWITCH 148LFBGA
Manufacturer
Pericom Semiconductor
Series
GreenPacket™r
Datasheet
1.PI7C9X20404GPBNBE.pdf
(79 pages)
Specifications of PI7C9X20404GPBNBE
Applications
Data Transport
Interface
Advanced Configuration Power Interface (ACPI)
Package / Case
148-LFBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI7C9X20404GPBNBE
Manufacturer:
RICHTEK
Quantity:
770
6.1.4 MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS
June 2009 – Revision 1.6
Pericom Semiconductor
ADDRESS
0Ah
0Ch
00h
02h
04h
06h
08h
Reserved
Reserved
Reserved
Reserved
15 – 8
PCI CFG
OFFSET
00h ~ 01h
02h ~ 03h
144h (Port 0~3)
144h: Bit [0]
ECh (Port 0~3)
ECh: Bit [14:12]
ECh: Bit [17:15]
B4h (Port 0~3)
B4h:Bit [5]
3Ch (Port 1~3)
3Ch: Bit [8]]
BCh: Bit [15:0]
BCh: Bit [31:16]
E4h(Port 0~3)
E4h: Bit 0
ECh(Port 0~3)
ECh: Bit[11:10]
E4h(Port 0~3)
E4h: Bit[15]
B0h(port 0~3)
B0h : Bit [14]
B0h(port 0~3)
B0h : Bit [15]
B4h(port 0~3)
B4h : Bit [15]
B0h(port 0~3)
B0h : Bit [13]
A8h(Port 0~3)
Bit [6]
Bit [0]
Bit [2:1]
Bit [3]
Bit [4]
PHY Parameter for Port 2
PHY Parameter for Port 3
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
EEPROM signature – 1516h
Vendor ID
Device ID
Extended VC Count for Port 0 ~ 3
Link Capability for Port 0 ~ 3
Switch Mode Operation for Port 0
Interrupt pin for Port 1 ~ 3
Subsystem Vender ID
Subsystem ID
Max_Payload_Size Support for Port 0 ~ 3
ASPM Support for Port 0 ~ 3
Role_Base Error Reporting for Port 0 ~ 3
MSI Capability Disable for Port 0~3
AER Capability Disable for Port 0~3
Compliance Pattern Parity Control Disable for Port 0~3
Power Management Capability Disable for Port 0~3
RefClk ppm Difference for Port 0 ~ 3
PM Control Para/Rx Polarity for Port 0
PM Control Para/Rx Polarity for Port 1
PM Control Para/Rx Polarity for Port 2
PM Control Para/Rx Polarity for Port 3
Page 24 of 79
Bit [0]: It represents the supported VC count other than the
default VC
Bit [3:1]: It represents L0s Exit Latency for all ports
Bit [6:4]: It represents L1 Exit Latency for all ports
Bit [8]: no ordering on packets for different egress port mode
Bit [9]: no ordering on different tag of completion mode
Bit [10]: Store and Forward
Bit [12:11]: Cut-through Threshold
Bit [13] : Port arbitrator Mode
Bit [14]: Credit Update Mode
Bit [15]: Set when INTA is requested for interrupt resource
Bit [0]: Indicated the maximum payload size that the device can
support for the TLP
Bit [2:1] : Indicate the level of ASPM supported on the PCIe link
Bit [3] : Indicate implement the role-base error reporting
Bit [4] : Disable MSI capability
Bit [5] : Disable AER capability
Bit [6] : Disable compliance pattern parity
Bit [7] : Disable Power Management Capability
7 – 0
4Port-4Lane PCI Express Switch
GreenPacket
BYTE OFFSET
PI7C9X20404GP
9Ah
A0h
A2h
A4h
A6h
9Ch
9Eh
94h
96h
98h
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