PI7C9X20404GPBNBE Pericom Semiconductor, PI7C9X20404GPBNBE Datasheet - Page 26

• Manufacturer Part Number: PI7C9X20404GPBNBE
• Description: IC PCIE PACKET SWITCH 148LFBGA
• Manufacturer: Pericom Semiconductor
• Series: GreenPacket™r

Specifications of PI7C9X20404GPBNBE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 148-LFBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

June 2009 – Revision 1.6
Pericom Semiconductor
ADDRESS
22h
24h
26h
32h
34h
PCI CFG
OFFSET
154h (Port 0)
154h: Bit [7:1]
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
144h (Port 1)
144h: Bit [4]
ECh (Port 1)
ECh: Bit [25:24]
154h (Port 1)
154h: Bit [7:1]
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
144h (Port 2)
144h: Bit [4]
ECh (Port 2)
ECh: Bit [25:24]
154h (Port 2)
154h: Bit [7:1]
E0h (Port 3)
E0h: Bit [24]
F0h (Port 3)
F0h: Bit [28]
80h (Port 3)
80h: Bit[21]
144h (Port 3)
144h: Bit [4]
ECh (Port 3)
ECh: Bit [25:24]
154h (Port 3)
154h: Bit [7:1]
F4h (Port 1)
F4h: Bit [15:0]
F4h (Port 2)
F4h: Bit [15:0]
DESCRIPTION
VC0 TC/VC Map for Port 0
PCIe Capability Slot Implemented for Port 1
Slot Clock Configuration for Port 1
Device specific Initialization for Port 1
LPVC Count for Port 1
Port Number for Port 1
VC0 TC/VC Map for Port 1
PCIe Capability Slot Implemented for Port 2
Slot Clock Configuration for Port 2
Device specific Initialization for Port 2
LPVC Count for Port 2
Port Number for Port 2
VC0 TC/VC Map for Port 2
PCIe Capability Slot Implemented for Port 3
Slot Clock Configuration for Port 3
Device specific Initialization for Port 3
LPVC Count for Port 3
Port Number for Port 3
VC0 TC/VC Map for Port 3
Slot Capability 0 of Port 1
Slot Capability 0 of Port 2
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Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 1
Bit [1]: When set, the component uses the clock provided on the
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 1
Bit [5:4]: It represents the logic port numbering for physical port
1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 2
Bit [5:4]: It represents the logic port numbering for physical port
2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 3
Bit [1]: When set, the component uses the clock provided on the
Bit [2]: When set, the DSI is required
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 3
Bit [5:4]: It represents the logic port numbering for physical port
3
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the low word of slot capability register
Connector
Connector
4Port-4Lane PCI Express Switch
GreenPacket
PI7C9X20404GP
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