SCANSTA101SM/NOPB National Semiconductor, SCANSTA101SM/NOPB Datasheet - Page 6

• Manufacturer Part Number: SCANSTA101SM/NOPB
• Description: IC TEST MASTER LOW-VOLT 49FBGA
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM/NOPB

• Applications: Testing Equipment
• Interface: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 49-FBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCANSTA101SM; *SCANSTA101SM/NOPB; SCANSTA101SM

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f
t
SERIAL SCAN INTERFACE (SSI)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX
RELEASE
D5
D6
D7
D8
D9
D10
D11
EN1
DIS1
EN2
DIS2
DIS3
S2
H2
Symbol
Symbol
Note 3: Due to uncertainty in the relationship of the STB placement to the system clock, SCK, the STB may be detected during the current or the next SCK cycle.
Note 4: An absolute maximum delay can be calculated as: (Max # SCK) x (SCK Period) + t
For example, for t
maximum delay is (3 x 100ns) + 11.5, or 311.5ns.
Clock Frequency, SCK
Release Time, RST to STB
Propagation Delay
SCK to TCK_SM
Propagation Delay
SCK to TDO_SM
Propagation Delay
SCK to TMS_SM
Propagation Delay - tpLH
SCK to TRIST_SM
Propagation Delay - tpHL
SCK to TRIST_SM
Propagation Delay
SCK to TDO_SM disable
Propagation Delay
SCK to TDO_SM enable
Enable Delay
OE low to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
Disable Delay
OE high to TCK_SM, TDO_SM, TMS_SM, or
TRST0_SM
Enable Delay
OE low to TRIST_SM
Disable Delay
OE high to TRIST_SM
Disable Delay
RST low to TRST0_SM
Setup Time
SCK to TDI_SM
Hold Time
SCK to TDI_SM
D1
(STB low to DTACK low, register write), the # SCK cycles is 2 or 3 and the delay, t
Parameter
Parameter
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Conditions
6
Conditions
D
.
D
(Note
, is 11.5ns. For a SCK with a 100ns period, the absolute
# of SCK
3,
2
Note
4)
Min
3.5
2.0
Min
11.5
12.0
12.5
15.0
12.5
12.5
14.0
12.0
11.0
10.0
11.5
12.5
Max
Max
66
Units
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns