SCANSTA101SM/NOPB National Semiconductor, SCANSTA101SM/NOPB Datasheet - Page 27

• Manufacturer Part Number: SCANSTA101SM/NOPB
• Description: IC TEST MASTER LOW-VOLT 49FBGA
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM/NOPB

• Applications: Testing Equipment
• Interface: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 49-FBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCANSTA101SM; *SCANSTA101SM/NOPB; SCANSTA101SM

16/32 bit Mode
TDO_SM Ctrl<11:10>
Sync Bit Length "x"
Default TDO Value
Debug Mode
ScanBridge Support Initiate/
Release
TRST
Reset
Test Loop-Back<1:0>
Bit(s)
14:10
11:10
9:7
1:0
15
6
5
4
3
2
'00'
'01'
'10'
'11'
'00'
'01'
'10'
'11'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
16/32 bit Mode
Reserved
TDO_SM Ctrl
Sync Bit Length
Default TDO Value
Debug Mode
ScanBridge Support Initiate/ Release
TRST
Reset
Test Loop-Back
Selects 16-bit or 32-bit external interface mode
32-bit external interface mode (used in macro form only)
16-bit external interface mode
TDO_SM Control bits
Hold previous value
Default TDO Value
Default TDO Value
High impedance
Sync Bit Length bits represents the number of sync bits to be used when the Sync Bit
Support Enable bit (17 in the Macro Structure) is set. The value "x" is the binary encoded
numeric value.
The value in this register will be sent out on the TDO_SM pin when performing a BIST or
a STATE Macro.
Drive TDO_SM to one.
Drive TDO_SM to zero.
Control bit to put SCANSTA101 in debug mode
Debug mode.
Normal mode.
ScanBridge support enable
Enable ScanBridge support
Disable ScanBridge support
Processor initiated ScanMaster test reset (on TRST0_SM and TRST1_SM_N). Bit is
cleared by a processor write.
Set TRST outputs low (active) and reset SSI logic.
Set TRST outputs high
Processor commanded synchronous reset to the serial scan logic for 2 clocks. This bit is
self clearing.
Reset the entire chip.
Release serial scan logic reset
Test loop-back mode bits
Normal operation
Loop-back TDO_SM to TDI_SM
Loop-back TMS_SM to TDI_SM
All Dot1 (1149.1) pins placed in SEU tolerant safe mode with: TMS_SM = 1, TCK_SM =
0, TDO_SM = Z, TRST0_SM = 0
TABLE 22. Setup Register (SETUPR) ($04)
Field
27
Address Offset
0
0
0
0
0
0
0
0
0
0
Reset Value
000b
00h
00b
11b
0b
1b
0b
0b
0b
0b
Reset Source
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
SYS_RST
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