SCANSTA101SM/NOPB National Semiconductor, SCANSTA101SM/NOPB Datasheet - Page 22

• Manufacturer Part Number: SCANSTA101SM/NOPB
• Description: IC TEST MASTER LOW-VOLT 49FBGA
• Manufacturer: National Semiconductor

Specifications of SCANSTA101SM/NOPB

• Applications: Testing Equipment
• Interface: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 49-FBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *SCANSTA101SM; *SCANSTA101SM/NOPB; SCANSTA101SM

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Signal Name
TDO
TDI
TMS
TCK
TRST
SAFE MODE
This device implements the following design rules to provide
Single Event Upset/Single Event Error (SEU/SEE) protection:
•
•
•
CLOCK GENERATION AND DISTRIBUTION
Input Clock (SCK): Up to 66 MHz
Output Clock (TCK_SM): TCK_SM is a divided, registered
version of SCK.
Triple modular redundancy (TMR) for TRST0_SM and
TRST1_SM outputs with the help of a TMR D flip-flop .
After reset all scan interface outputs are driven to SEU
tolerant safe values as shown below:
TMS_SM = 1
TCK_SM = 0
TDO_SM = high-Z
TRST0_SM = 0
TRST1_SM = 0
The EXTEST and the HIGHZ outputs from the JTAG TAP
controller are gated with TRST to protect the boundary
scan cells from inadvertently entering the test mode.
No. of
Bits
1
1
1
1
1
Pin Type
I,U,H
I,U
I,U
O
I
FIGURE 14. SSI Timing Diagram with Clock Divider set to 8
TABLE 17. SCANSTA101 1149.1 Signal Descriptions
Driver Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
22
up to 25
up to 25
up to 25
up to 25
Freq.
MHz
N/A
•
•
RESET STRATEGY
The incoming external hardware reset (RST) will be synchro-
nized to the incoming clock (SCK) and is combined with the
soft reset to generate a synchronized internal reset
(SYS_RST_N). During operation, the chip can be reset by
writing a '1' to the Reset bit in the Setup register. All logic
throughout the device will be initialized, all control and status
registers will be in a known default state, all PPI memory ad-
dress pointers will default to their respective base addresses,
the SSI memory pointer will default to zero, the Tap Tracker
will be reset to TLR, and the clock division counter will be
initialized to all zeroes after deassertion of the internal reset.
The Reset bit in the Setup register is self clearing. The TRST
bit in the Setup register, when set, resets the SSI logic and
drives the TRST0_SM and TRST1_SM to zero.
Selectable: to 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, and 1/128 of
SCK.
Frequency: up to 25 MHz
SCANSTA101 Test Data Out
SCANSTA101 Test Data In (pullup (U))
SCANSTA101 Test Mode Select (pullup (U))
SCANSTA101 Test Clock
SCANSTA101 Test Reset (pullup (U) & hysteresis (H))
Description
10121541