FIN1217MTDX Fairchild Semiconductor, FIN1217MTDX Datasheet - Page 18

• Manufacturer Part Number: FIN1217MTDX
• Description: IC SERIALIZER/DESERIAL 48-TSSOP
• Manufacturer: Fairchild Semiconductor
• Type: LVDS 21-Bit Serializer/Deserializerr

Specifications of FIN1217MTDX

• Function: Serializer/Deserializer
• Data Rate: 1.785Gbps
• Input Type: LVTTL
• Output Type: LVDS
• Number Of Inputs: 21
• Number Of Outputs: 3
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Number Of Drivers: 3
• Number Of Receivers: 21
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 65 C
• Mounting Style: SMD/SMT
• Supply Current: 55 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FIN1217MTDX; FIN1217MTDXTR

© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
AC Loadings and Waveforms
Note: t
Note: This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
worst jitter ±ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
RSKM
is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to
the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 11).
The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources.
Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from
graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V
with 100mV noise (V
Figure 22.
CC
noise frequency <2MHz).
(Continued)
Figure 23.
Receiver LVDS Input Skew Margin
18
Jitter Pattern
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CC
range