ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 62

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

ADV7181
MPU PORT DESCRIPTION
The ADV7181 supports a 2-wire (I
face. Two inputs, serial data SDA and serial clock SCLK, carry
information between the ADV7181 and the system I
controller. Each slave device is recognized by a unique address.
The ADV7181’s I
the decoder and to read back captured VBI data. The ADV7181
has four possible slave addresses for both read and write
operations, depending on the logic level on the ALSB pin. These
four unique addresses are shown in Table 168. The ADV7181’s
ALSB pin controls Bit 1 of the slave address. By altering the
ALSB, it is possible to control two ADV7181s in an application
without having a conflict with the same slave address. The LSB
(Bit 0) sets either a read or write operation. Logic 1 corresponds
to a read operation; Logic 0 corresponds to a write operation.
Table 168. I
ALSB
0
0
1
1
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing
a start condition, which is defined by a high-to-low transition
on SDA while SCLK remains high. This indicates that an
address/data stream follows. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDA and SCLK lines, waiting for
the start condition and the correct transmitted address. The
R/W bit determines the direction of the data. Logic 0 on the
2
C Address for ADV7181
SEQUENCE
SEQUENCE
R/W
0
1
0
1
2
WRITE
C port allows the user to set up and configure
READ
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR
Slave Address
0x40
0x41
0x42
0x43
SCLOCK
2
SDATA
C-compatible) serial inter-
LSB = 0
A(S)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
START ADDR
S
SUB ADDR
SUB ADDR
1–7
2
C master
R/W
8
Figure 36. Read and Write Sequence
A(S)
A(S) S
ACK
Figure 35. Bus Data Transfer
9
Rev. B | Page 62 of 104
SUBADDRESS
DATA
SLAVE ADDR
1–7
LSB = 1
8
A(S)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
ACK
LSB of the first byte means that the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADV7181 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. The ADV7181 has 196 subaddresses
to enable access to the internal registers. It therefore interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a stop condition. The user
can also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLK
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7181 does not issue an acknowledge and returns to the
idle condition.
If in auto-increment mode the user exceeds the highest
subaddress, the following action is taken:
1.
2.
A(S)
9
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDA line is not pulled
low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7181, and the part returns to the idle condition.
DATA
1–7
DATA
8
DATA
ACK
A(M)
9
STOP
P
A(S) P
DATA
A(M) P