ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 32

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

ADV7181
Luma Gain
LAGC[2:0] Luma Automatic Gain Control,
Address 0x2C [7:0]
The luma automatic gain control mode bits select the mode of
operation for the gain control in the luma path.
There are ADI internal parameters to customize the peak white
gain control. Contact ADI for more information.
Table 63. LAGC Function
LAGC[2:0]
000
001
010 (default)
011
100
101
110
111
LAGT[1:0] Luma Automatic Gain Timing, Address 0x2F [7:6]
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. This register has an effect only if the LAGC[2:0]
register is set to 001, 010, 011, or 100 (automatic gain control
modes).
If peak white AGC is enabled and active (see the
STATUS_1[7:0] Address 0x10 [7:0] section), the actual gain
update speed is dictated by the peak white AGC loop and, as a
result, the LAGT settings have no effect. As soon as the part
leaves peak white AGC, LAGT becomes relevant again.
The update speed for the peak white algorithm can be
customized by the use of internal parameters. Contact ADI
for more information.
Table 64. LAGT Function
LAGT[1:0]
00
01
10
11 (default)
Freeze gain.
Adaptive
Description
Manual fixed gain (use LMG[11:0]).
AGC (blank level to sync tip). No override
through white peak.
AGC (blank level to sync tip). Automatic
override through white peak.
Reserved.
Reserved.
Reserved.
Reserved.
Description
Slow (TC = 2 s)
Medium (TC = 1 s)
Fast (TC = 0.2 s)
Rev. B | Page 32 of 104
LG[11:0] Luma Gain, Address 0x2F [3:0]; Address 0x30 [7:0];
LMG[11:0] Luma Manual Gain, Address 0x2F [3:0];
Address 0x30 [7:0]
Luma gain [11:0] is a dual-function register:
•
•
•
Table 65. LG/LMG Function
LG[11:0]/LMG[11:0]
LMG[11:0] = X
LG[11:0]
Example
Program the ADV7181 into manual fixed gain mode with a
desired gain of 0.89
1.
2.
3.
4.
5.
If written to, a desired manual luma gain can be
programmed. This gain becomes active if the LAGC[2:0]
mode is switched to manual fixed gain.
Equation 1 shows how to calculate a desired gain.
If read back, this register returns the current gain value.
Depending on the setting in the LAGC [2:0] bits, this is
one of the following values:
o
o
Use Equation 1 to convert the gain:
0.89 × 2048 = 1822.72
Truncate to integer value:
1822.72 = 1822
Convert to hexadecimal:
1822d = 0x71E
Split into two registers and program:
Luma Gain Control 1 [3:0] = 0x7
Luma Gain Control 2 [7:0] = 0x1E
Enable Manual Fixed Gain Mode:
Set LAGC[2:0] to 000
Luma
Luma manual gain value (LAGC [2:0] set to luma
manual gain mode).
Luma automatic gain value (LAGC [2:0] set to any of
the automatic modes).
_
Gain
=
(
0
<
Read/Write
Write
Read
LG
2048
≤
4095
)
=
Description
Manual gain for luma
path
Actually used gain
0
...
2
(1)