LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 53

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Datasheet
SMSC LAN8710/LAN8710i
5.3.9.2
5.3.9.3
MODE[2:0]
000
001
010
100
101
011
110
111
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is
deasserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital
block is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in
Table
MODE[2:0] pins have no affect.
The LAN8710 mode may be configured using hardware configuration as summarized in
The user may configure the transceiver mode by writing the SMI registers.
The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in
MII/RMII Mode Selection
MII or RMII mode selection is latched on the rising edge of the internal reset (nRESET) based on the
strapping of the RXD2/RMIISEL pin. The default mode is MII with the internal pull-down resistor. To
select RMII mode, pull the RXD2/RMIISEL pin high with an external resistor to VDDIO.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
Power Down mode. In this mode the transceiver will
wake-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in
Register 18.7:5(see
to some other value and a soft reset must be
issued.
All capable. Auto-negotiation enabled.
5.21, the configuration of the 10/100 digital block is controlled by the register bit values, and the
MODE DEFINITIONS
Table
Table 5.41 Pin Names for Mode Bits
MODE BIT
MODE[0]
MODE[1]
MODE[2]
Table 5.40 MODE[2:0] Bus
5.30) must be configured
®
Technology in a Small Footprint
DATASHEET
COL/CRS_DV/MODE2
53
RXD0/MODE0
RXD1/MODE1
PIN NAME
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
X10X
0000
0001
1000
1001
1100
1100
N/A
Revision 1.0 (04-15-09)
REGISTER 4
[8,7,6,5]
0100
0100
1111
N/A
N/A
N/A
N/A
N/A
Table
Table
5.40.
5.41.