LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 15

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Datasheet
SMSC LAN8710/LAN8710i
RMIISEL
PHYAD2
SIGNAL
MODE0
MODE1
TXCLK
NAME
TXER/
RXD0/
RXD1/
RXD2/
RXD3/
TXEN
TXD2
TXD3
TXD4
nINT/
32-QFN
PIN #
24
25
18
21
20
10
11
9
8
Table 3.2 MII/RMII Signals (continued) 32-QFN (continued)
TYPE
IOPU
IOPU
IOPU
IOPD
IOPD
IPD
O8
I8
I8
Transmit Data 2: The MAC transmits data to the transceiver using this
signal in MII Mode.
Transmit Data 3: The MAC transmits data to the transceiver using this
signal in MII Mode.
nINT – Active low interrupt output. Place an external resistor pull-up to
VDDIO.
TXER – MII Transmit Error: When driven high, the 4B/5B encode process
substitutes the Transmit Error code-group (/H/) for the encoded data word.
This input is ignored in 10Base-T operation.
TXD4 – MII Transmit Data 4: In Symbol Interface (5B Decoding) mode, this
signal becomes the MII Transmit Data 4 line, the MSB of the 5-bit symbol
code-group.
Transmit Enable: Indicates that valid data is presented on the TXD[3:0]
signals, for transmission. In RMII Mode, only TXD[1:0] have valid data.
Transmit Clock: Used to latch data from the MAC into the transceiver.
RXD0 – Receive Data 0: Bit 0 of the 4 data bits that are sent by the
transceiver in the receive path.
MODE0 – PHY Operating Mode Bit 0: set the default MODE of the PHY.
RXD1 – Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY
in the receive path.
MODE1 – PHY Operating Mode Bit 1: set the default MODE of the PHY.
RXD2 – Receive Data 2: Bit 2 of the 4 data bits that are sent by the
transceiver in the receive path.
RMIISEL – MII/RMII Mode Selection: Latched on the rising edge of the
internal reset (nRESET) based on the following strapping:
RXD3 – Receive Data 3: Bit 3 of the 4 data bits that are sent by the
transceiver in the receive path.
PHYAD2 – PHY Address Bit 2: set the SMI address of the transceiver.
This signal should be grounded in RMII Mode.
This signal should be grounded in RMII Mode.
See
the function for this pin.
TXD4 is not used in RMII Mode.
This signal is mux’d with nINT
MII (100BT): 25MHz
MII (10BT): 2.5MHz
This signal is not used in RMII Mode.
See
See
The RXD2 signal is not used in RMII Mode.
By default, MII mode is selected.
Pull this pin high to VDDIO with an external resistor to select RMII mode,
This signal is not used in RMII Mode.
This signal is mux’d with PHYAD2
See
Section 4.10
Section 5.3.9.2
Section 5.3.9.2
Section 5.3.9.1
®
Technology in a Small Footprint
DATASHEET
15
for information on how nINTSEL is used to determine
for information on the MODE options.
for information on the MODE options.
for information on the ADDRESS options.
DESCRIPTION
Revision 1.0 (04-15-09)