LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 44

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

Revision 1.0 (04-15-09)
ADDRESS
ADDRESS
ADDRESS
18.13:8
26.15:0
18.7:5
18.4:0
17.5:4
18.15
18.14
17.6
17.3
17.2
17.1
17.0
Good Link Status
Sym_Err_Cnt
ENERGYON
PHYADBP
Reserved
MIIMODE
Reserved
Reserved
Reserved
PHYAD
ALTINT
NAME
MODE
NAME
NAME
Force
Table 5.29 Register 17 - Mode Control/Status (continued)
Table 5.31 Register 26 - Symbol Error Counter
Write as 0, ignore on read.
MII Mode: set the mode of the digital interface, as
described in
0 – MII interface.
1 – RMII interface
Write as 0, ignore on read.
Transceiver Mode of operation. Refer to
5.3.9.2, "Mode Bus – MODE[2:0]," on page 53
more details.
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to
PHYAD[2:0]," on page 52
Alternate Interrupt Mode.
0 = Primary interrupt system enabled (Default).
1 = Alternate interrupt system enabled.
See
Write as 0, ignore on read.
1 = PHY disregards PHY address in SMI access
0 = normal operation;
1 = force 100TX- link active;
Note:
ENERGYON – indicates whether energy is detected
on the line (see
Power-Down," on page
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Write as 0. Ignore on read.
100Base-TX receiver-based error register that
increments when an invalid code symbol is received
including IDLE symbols. The counter is incremented
only once per packet, even when the received packet
contains more than one symbol error. The 16-bit
register counts up to 65,536 (2
if incremented beyond that value. This register is
cleared on reset, but is not cleared by reading the
register. It does not increment in 10Base-T mode.
Table 5.30 Register 18 - Special Modes
Section 5.3.9.1, "Physical Address Bus -
write.
Section 5.2, "Interrupt Management," on page
This bit should be set only during lab testing
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
DATASHEET
Section
Section 5.3.5.2, "Energy Detect
DESCRIPTION
DESCRIPTION
DESCRIPTION
44
5.3.9.3:
50); it goes to “0” if no valid
for more details.
16
) and rolls over to 0
Section
for
47.
SMSC LAN8710/LAN8710i
®
MODE
MODE
MODE
NASR
NASR
NASR
NASR
Technology in a Small Footprint
RW,
RW,
RW,
RW,
RW
RW
RW
RW
RW
RO
RW
RO
DEFAULT
DEFAULT
DEFAULT
000000
PHYAD
Datasheet
XXX
00
0
0
X
0
0
0
X
0