LAN8710A-EZK SMSC, LAN8710A-EZK Datasheet - Page 52

• Manufacturer Part Number: LAN8710A-EZK
• Description: TXRX ETHERNET 10/100 MII/RMII
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8710A-EZK

• Number Of Drivers/receivers: 4/4
• Protocol: MII, RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1079; LAN8710A-EZK

Revision 1.0 (04-15-09)
5.3.8.3
5.3.9
5.3.9.1
Ethernet
10/100
MAC
Connector Loopback
The LAN8710/LAN8710i maintains reliable transmission over very short cables, and can be tested in
a connector loopback as shown in
transmit signals an the output of the transformer back to the receiver inputs, and this loopback will
work at both 10 and 100.
Configuration Signals
The hardware configuration signals are sampled during the power-on sequence to determine the
physical address and operating mode.
Physical Address Bus - PHYAD[2:0]
The PHYAD[2:0] bits are driven high or low to give each PHY a unique address. This address is
latched into an internal register at the end of a hardware reset. In a multi-transceiver application (such
as a repeater), the controller is able to manage each transceiver via the unique address. Each
transceiver checks each management data frame for a matching address in the relevant bits. When a
match is recognized, the transceiver responds to that particular frame. The PHY address is also used
to seed the scrambler. In a multi-Transceiver application, this ensures that the scramblers are out of
synchronization and disperses the electromagnetic radiation across the frequency spectrum.
The LAN8710 SMI address may be configured using hardware configuration to any value between 0
and 7. The user can configure the PHY address using Software Configuration if an address greater
than 7 is required. The PHY address can be written (after SMI communication at some address is
established) using the 10/100 Special Modes register (bits18.[4:0]).
The PHYAD[2:0] hardware configuration pins are multiplexed with other signals as shown in
Table
The LAN8710 may be configured to disregard the PHY address in SMI access write by setting the
register bit 17.3 (PHYADBP).
TXD
5.39.
RXD
Digital
Ethernet Transceiver
Figure 5.3 Connector Loopback Block Diagram
Table 5.39 Pin Names for Address Bits
ADDRESS BIT
SMSC
PHYAD[0]
PHYAD[1]
PHYAD[2]
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR
Analog
DATASHEET
Figure
52
5.3. An RJ45 loopback cable can be used to route the
RXCLK/PHYAD1
RXER/PHYAD0
RXD3/PHYAD2
PIN NAME
TX
RX
XFMR
RJ45 Loopback Cable.
Created by connecting pin 1 to pin 3
and connecting pin 2 to pin 6.
SMSC LAN8710/LAN8710i
®
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Technology in a Small Footprint
Datasheet