Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 167
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Enhanced Serial Peripheral Interface
Architecture
PS028702-1210
The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface)
and Inter IC Sound (I
The features of the ESPI include:
•
•
•
•
•
•
•
The ESPI is a full-duplex, synchronous, character-oriented channel that supporting a four-
wire interface (serial clock, transmit and receive data and Slave select). The ESPI block
consists of a shift register, transmit and receive data buffer registers, a baud rate (clock)
generator, control/status registers and a control state machine. Transmit and receive trans-
fers are in sync as there is a single shift register for both transmit and receive data. Fig-
ure 25 displays a block diagram of the ESPI.
Full-duplex, synchronous, character-oriented communication
Four-wire interface (SS, SCK, MOSI, MISO)
Transmit and receive buffer registers to enable high throughput
Transfer rates up to a maximum of one-fourth the system clock frequency when in
SLAVE mode
Error detection
Dedicated programmable baud rate generator (BRG)
Data transfer control through polling, interrupt, or DMA
2
S) modes of operation.
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
Product Specification
145
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