Z16FMC28AG20SG Zilog, Z16FMC28AG20SG Datasheet - Page 124
Z16FMC28AG20SG
Manufacturer Part Number
Z16FMC28AG20SG
Description
Microcontrollers (MCU) 16BIT 128K FL 4KRAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC28AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC28AG20SG
Manufacturer:
Zilog
Quantity:
176
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Table 66. PWM Output Control Register (PWMOUT)
Table 67. Current-Sense Sample and Hold Control Register (CSSHR0 and CSSHR1)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bit Position
[7,6]
Reserved
[5, 3, 1]
OUT2L/
OUT1L/
OUT0L
[4, 2, 0]
OUT2H/
OUT1H/
OUT0H
Bits
Field
RESET
R/W
ADDR
Bit Position
[7]
SHPOL
Current-Sense Sample and Hold Control Registers
Reserved Reserved
SHPOL
R/W
R
7
0
7
0
The current-sense sample/hold control register defines the behavior of the dedicated cur-
rent sense sample and hold inputs to the ADC from the operational amplifier. These input
hold the current input value whenever all high-side outputs or all low-side outputs are in
the on-state. The register bits control which PWM outputs must be asserted to activate the
internal hold signal. Disabling the HEN, LEN, NHEN and NLEN bits allows software
control of the input sample/hold by writing the SHPOL bit.
Value (H)
Value (H)
0
1
0
1
0
1
HEN
R/W
R
6
0
6
0
Sample Hold Polarity
Hold when terms are active.
Hold when terms are not active.
Description
Description
Must be 0.
PWM 2L/1L/0L output configuration
PWM 2L/1L/0L output signal is enabled and controlled by PWM.
PWM 2L/1L/0L output signal is in low-side off-state.
PWM 2H/1H/0H output configuration
PWM 2H/1H/0H output signal is enabled and controlled by PWM.
PWM 2H/1H/0H output signal is in high-side off-state.
OUT2L
NHEN
R/W
R/W
5
0
5
0
P R E L I M I N A R Y
FF_E38AH and FF_E38BH
OUT2H
LEN
R/W
R/W
4
0
4
0
FF_E387H
OUT1L
NLEN
R/W
R/W
Z16FMC Series Motor Control MCUs
3
0
3
0
SHPWM2 SHPWM1 SHPWM0
OUT1H
R/W
R/W
2
0
2
0
Multi-Channel PWM Timer
Product Specification
OUT0L
R/W
R/W
1
0
1
0
OUT0H
R/W
R/W
0
0
0
0
102
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