STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 99

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
9.13.2
31
15
Reserved
Bits [12:10] SC_RXSSEL: Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode)
30
14
Serial DMA status register (SCx_DMASTAT)
Address offset: 0xC82C (SC1_DMASTAT) and 0xC02C (SC2_DMASTAT)
Reset value:
Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA
Bit 0 SC_RXLODA: Setting this bit loads DMA receive buffer A addresses and allows the DMA
Bit 9 SC_RXFRMB: This bit is set when DMA receive buffer B reads a byte with a frame error from
Bit 8 SC_RXFRMA: This bit is set when DMA receive buffer A reads a byte with a frame error from
Bit 7 This bit is set when DMA receive buffer B reads a byte with a parity error from the receive FIFO.
29
13
controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
controller to start processing receive buffer A. If both buffer A and B are loaded simultaneously,
buffer A will be used first. This bit is cleared when DMA completes. Writing a zero to this bit has
no effect.
Reading this bit returns DMA buffer status:
0: DMA processing is complete or idle.
1: DMA processing is active or pending.
when nSSEL deasserts. Cleared when a receive buffer is loaded and when the receive DMA is
reset.
the receive FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
the receive FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset.
(SC1 in UART mode only)
It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
0: No count was saved because nSSEL did not deassert.
2: Buffer A's count was saved, nSSEL deasserted once.
3: Buffer B's count was saved, nSSEL deasserted once.
6: Buffer A's count was saved, nSSEL deasserted more than once.
7: Buffer B's count was saved, nSSEL deasserted more than once.
1, 4, 5: Reserved.
28
12
SC_RXSSEL
27
11
r
0x0000 0000
26
10
SC_RX
FRMB
25
9
r
Doc ID 16252 Rev 8
SC_RX
FRMA
24
8
r
Reserved
SC_RX
PARB
23
7
r
SC_RX
PARA
22
6
r
SC_RX
OVFB
21
5
r
SC_R
XOVF
20
A
4
r
SC_TX
ACTB
19
3
r
SC_TX
ACTA
Serial interfaces
18
2
r
SC_RX
ACTB
17
1
r
99/209
SC_RX
ACTA
16
0
r