STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 133

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
10.1.14
Note:
Figure 43. Control circuit in External clock mode 2 + Trigger mode
Timer synchronization
The two timers can be linked together internally for timer synchronization or chaining. A
timer configured in Master mode can reset, start, stop or clock the counter of the other timer
configured in Slave mode.
Figure 44
blocks.
Using one timer as prescaler for the other timer
For example, to configure Timer 1 to act as a prescaler for Timer 2 (see
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If OCy is selected on Timer 1 as trigger output (TIM_MMS = 1xx), its rising edge is used to
clock the counter of Timer 2.
Figure 44. Master/slave timer example
Configure Timer 1 in Master mode so that it outputs a periodic trigger signal on each
update event. Writing TIM_MMS = 010 in the TIM1_CR2 register causes a rising edge
to be output on TRGO each time an update event is generated.
To connect the TRGO output of Timer 1 to Timer 2, configure Timer 2 in slave mode
using ITR0 as an internal trigger. Select this through the TIM_TS bits in the
TIM2_SMCR register (writing TIM_TS = 000).
Put the slave mode controller in external clock mode 1 (write TIM_SMS = 111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which corresponds to the Timer 1 counter overflow).
Finally both timers must be enabled by setting their respective TIM_CEN bits
(TIMx_CR1 register).
presents an overview of the trigger selection and the master mode selection
Doc ID 16252 Rev 8
General-purpose timers
Figure
44):
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