STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 100

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial interfaces
9.13.3
9.13.4
100/209
31
15
31
15
Reserved
Reserved
30
14
30
14
Bits [12:0] SC_TXBEGA: DMA transmit buffer A start address.
Transmit DMA begin address register A (SCx_TXBEGA)
Address offset: 0xC810 (SC1_TXBEGA) and 0xC010 (SC2_TXBEGA)
Reset value:
Transmit DMA begin address register B (SCx_TXBEGB)
Address offset: 0xC818 (SC1_TXBEGB) and 0xC018 (SC2_TXBEGB)
Reset value:
Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO.
Bit 5 This bit is set when DMA receive buffer B was passed an overrun error from the receive FIFO.
Bit 4 This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO.
Bit 3 This bit is set when DMA transmit buffer B is active.
Bit 2 This bit is set when DMA transmit buffer A is active.
Bit 1 This bit is set when DMA receive buffer B is active.
Bit 0 This bit is set when DMA receive buffer A is active.
29
13
29
13
It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1 in UART
mode only)
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer B was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer B is loaded and
when the receive DMA is reset.
Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled
up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was
passed up to the DMA and flagged with this bit. Cleared the next time buffer A is loaded and
when the receive DMA is reset.
28
12
28
12
27
11
27
11
0x2000 0000
0x2000 0000
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
23
23
7
7
SC_TXBEGA
SC_TXBEGB
22
22
6
6
rw
rw
21
21
5
5
STM32W108CB, STM32W108HB
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
16
16
0
0