STM32W108CBU63TR STMicroelectronics, STM32W108CBU63TR Datasheet - Page 143

• Manufacturer Part Number: STM32W108CBU63TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU63TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
10.3.4
31
15
30
14
Bits [2:0] TIM_SMS: Slave Mode Selection
Timer x event generation register (TIMx_EGR)
Address offset: 0xE014 (TIM1) and 0xF014 (TIM2)
Reset value:
29
13
When external signals are selected the active edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input.
000: Slave mode disabled.
If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock.
001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.
010: Encoder mode 2. Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.
011: Encoder mode 3. Counter counts up/down on both TI1FP1 and TI2FP2 edges depending
on the level of the other input.
100: Reset Mode. Rising edge of the selected trigger signal (TRGI) >reinitializes the counter
and generates an update of the registers.
101: Gated Mode. The counter clock is enabled when the trigger signal (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both starting and stopping
the counter are controlled.
110: Trigger Mode. The counter starts at a rising edge of the trigger TRGI (but it is not reset).
Only starting the counter is controlled.
111: External Clock Mode 1. Rising edges of the selected trigger (TRGI) clock the counter.
Note: Gated mode must not be used if TI1F_ED is selected as the trigger input
28
12
Reserved
(TIM_TS=100). TI1F_ED outputs 1 pulse for each transition on TI1F, whereas gated
mode checks the level of the trigger signal.
27
11
0x0000 0000
26
10
25
9
Doc ID 16252 Rev 8
24
8
Reserved
23
7
TIM_T
22
G
w
6
Reserv
21
ed
5
TIM_C
C4G
20
w
4
General-purpose timers
TIM_C
C3G
19
w
3
TIM_C
C2G
18
w
2
TIM_C
C1G
17
w
1
143/209
TIM_U
16
G
w
0