PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 33

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

3.0
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X CPU have a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for digital
signal processing. The CPU has a 24-bit instruction
word, with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses, and the table instructions.
Overhead free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X devices have six-
teen 16-bit Working registers in the programmer’s
model. Each of the Working registers can act as a data,
address or address offset register. The 16th Working
register (W15) operates as a software Stack Pointer for
interrupts and calls.
3.2
The instruction set for dsPIC33EPXXXGP50X and
dsPIC33EPXXXMC20X/50X devices has two classes of
instructions: the MCU class of instructions and the DSP
class
PIC24EPXXXGP/MC20X devices has the MCU class of
instructions only and does not support DSP instructions.
These two instruction classes are seamlessly integrated
into the architecture and execute from a single execution
unit. The instruction set includes many addressing modes
and was designed for optimum C compiler efficiency.
 2011-2012 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
of
2: Some registers and associated bits
CPU
Registers
Instruction Set
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70359) in the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
instructions.
the
The
dsPIC33EPXXXGP50X,
instruction
families
set
and
of
in
for
3.3
The base data space can be addressed as 4K words or
8 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear data space. On dsPIC33EPXXXMC20X/
50X and dsPIC33EPXXXGP50X devices, certain DSP
instructions operate through the X and Y AGUs to sup-
port dual operand reads, which splits the data address
space into two parts. The X and Y data space boundary
is device specific.
The upper 4 Kbytes of the data space memory map can
optionally be mapped into program space at any 16K
program word boundary. The program-to-data-space
mapping feature, known as Program Space Visibility
(PSV), lets any instruction access program space as if
it were data space. Moreover, the Base Data Space
address is used in conjunction with a read or write page
register (DSRPAG or DSWPAG) to form an Extended
Data Space (EDS) address. The EDS can be
addressed as 8 Mwords or 16 Mbytes. Refer to
Section 3. “Data Memory” (DS70595) and Section 4.
“Program Memory” (DS70613) in the “dsPIC33E/
PIC24E Family Reference Manual” for more details on
EDS, PSV and table accesses.
On
dsPIC33EPXXXGP50X
circular buffers (Modulo Addressing) are supported in
both X and Y address spaces. The Modulo Addressing
removes the software boundary-checking overhead for
DSP algorithms. The X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reverse Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms. PIC24EPXXXGP/MC20X devices do not
support Modulo and Bit-Reverse Addressing.
3.4
The CPU supports these addressing modes:
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
Addressing mode group, depending upon its functional
requirements. As many as six Addressing modes are
supported for each instruction.
Data Space Addressing
Addressing Modes
dsPIC33EPXXXMC20X/50X
devices,
DS70657F-page 33
overhead-free
and