PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 140

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 8-1:
DS70657F-page 140
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-6
bit 5-4
bit 3-2
bit 1-0
R/W-0
CHEN
U-0
—
CHEN: Channel Enable bit
1 = Channel enabled
0 = Channel disabled
SIZE: Data Transfer Size bit
1 = Byte
0 = Word
DIR: Transfer Direction bit (source/destination bus select)
1 = Read from RAM address, write to peripheral address
0 = Read from Peripheral address, write to RAM address
HALF: Block Transfer Interrupt Select bit
1 = Initiate interrupt when half of the data has been moved
0 = Initiate interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0 = Normal operation
Unimplemented: Read as
AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect Addressing mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
Unimplemented: Read as
MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA buffer)
10 = Continuous, Ping-Pong modes enabled
01 = One-Shot, Ping-Pong modes disabled
00 = Continuous, Ping-Pong modes disabled
R/W-0
SIZE
U-0
—
DMA
X
CON: DMA CHANNEL
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
DIR
AMODE<1:0>
‘
‘
0
0
’
’
R/W-0
R/W-0
HALF
X
CONTROL REGISTER
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NULLW
R/W-0
U-0
—
U-0
U-0
—
—
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
MODE<1:0>
R/W-0
U-0
—
bit 8
bit 0