PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 256

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
REGISTER 17-3:
DS70657F-page 256
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
PCIIRQ
HS, RC-0
U-0
—
(1)
This status bit is only applicable to PIMOD<2:0> modes ‘011’ and ‘100’.
Unimplemented: Read as ‘0’
PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POSxCNT ≥ QEI1GEC
0 = POSxCNT < QEI1GEC
PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POSxCNT ≤ QEI1LEC
0 = POSxCNT > QEI1LEC
PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit
1 = POSxCNT was reinitialized
0 = POSxCNT was not reinitialized
PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has not occurred
VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred
0 = No Home event has occurred
HOMIEN: Home Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
PCIIEN
R/W-0
U-0
—
QEI1STAT: QEI STATUS REGISTER
HS = Set by Hardware
W = Writable bit
‘1’ = Bit is set
PCHEQIRQ PCHEQIEN PCLEQIRQ
VELOVIRQ
HS, RC-0
HS, RC-0
VELOVIEN
R/W-0
R/W-0
C = Cleared by Software
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HS, RC-0
HS, RC-0
HOMIRQ
PCLEQIEN
HOMIEN
R/W-0
R/W-0
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
POSOVIRQ
HS, RC-0
HS, RC-0
IDXIRQ
(1)
POSOVIEN
IDXIEN
R/W-0
R/W-0
bit 8
bit 0