DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 97

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
The
dsPIC33FJ16MC304 oscillator system provides:
• External and internal oscillator options as clock
FIGURE 7-1:
© 2007 Microchip Technology Inc.
Note:
sources
OSCO
SOSCO
OSCI
SOSCI
Note 1: See Figure 7-2 for PLL details.
OSCILLATOR
CONFIGURATION
This data sheet summarizes the features
of
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC33F
Family Reference Manual”. Please see
the Microchip web site (www.micro-
chip.com) for the latest dsPIC33F Family
Reference Manual sections.
dsPIC33FJ32MC202/204
Oscillator
TUN<5:0>
the
FRC
Primary Oscillator
Secondary Oscillator
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 OSCILLATOR SYSTEM DIAGRAM
dsPIC33FJ32MC202/204
Oscillator
LPRC
LPOSCEN
S1
S3
÷ 16
FRCDIV<2:0>
and
and
Preliminary
PLL
(1)
dsPIC33F
XTPLL, HSPLL,
ECPLL, FRCPLL
Clock Fail
• An on-chip Phase-Locked Loop (PLL) to scale the
• An internal FRC oscillator that can also be used
• Clock switching between various clock sources
• Programmable clock postscaler for system power
• A Fail-Safe Clock Monitor (FSCM) that detects
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
A simplified diagram of the oscillator system is shown
in Figure 7-1.
S7
XT, HS, EC
internal operating frequency to the required
system clock frequency
with the PLL, thereby allowing full-speed opera-
tion without any external clock generation hard-
ware
savings
clock failure and takes fail-safe measures
selection.
FRCDIV16
FRCDIVN
SOSC
LPRC
FRC
Clock Switch
NOSC<2:0> FNOSC<2:0>
S1/S3
S7
S0
S5
S4
S2
S6
÷ 2
Reset
DOZE<2:0>
DS70283B-page 95
WDT, PWRT,
Timer 1
FSCM
F
F
OSC
CY