DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 223

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

20.2
The
dsPIC33FJ16MC304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices
dsPIC33FJ16MC304 family incorporate an on-chip
regulator that allows the device to run its core logic from
V
The regulator provides power to the core from the other
V
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure 20-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 23-13 located in Section 23.1
“DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 20-1:
© 2007 Microchip Technology Inc.
DD
DD
Note 1:
.
pins. When the regulator is enabled, a low-ESR
On-Chip Voltage Regulator
,
in
STARTUP
it takes approximately 20 μs for the on-chip
C
F
These are typical operating voltages. Refer
to Table 23-13 located in Section 23.1 “DC
Characteristics” for the full operating
ranges of V
dsPIC33FJ32MC202/204
3.3V
the
is applied every time the device
dsPIC33FJ32MC202/204
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
DD
DD
DDCORE
SS
dsPIC33F
and V
STARTUP
/V
DDCORE
CAP
, code execution is
DDCORE
.
(1)
/V
CAP
and
and
Preliminary
pin
20.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage V
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, if enabled, contin-
ues to operate while in Sleep or Idle modes and resets
the device should VDD fall below the BOR threshold
voltage.
BOR: Brown-Out Reset
DDCORE
. The main purpose of
DS70283B-page 221