DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 158

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.14.4
Each of the Fault input pins has two modes of
operation:
• Latched Mode: When the Fault pin is driven low,
• Cycle-by-Cycle Mode: When the Fault input pin
The operating mode for each Fault input pin is selected
using the FLTAM control bits in the PxFLTACON
Special Function Registers.
Each of the Fault pins can be controlled manually in
software.
14.15 PWM Update Lockout
For a complex PWM application, the user application
may need to write up to three Duty Cycle registers and
the PWM Time Base Period register, PxTPER, at a
given time. In some applications, it is important that all
buffer registers be written before the new duty cycle
and period values are loaded for use by the module.
The PWM update lockout feature is enabled by setting
the UDIS control bit in the PWM1CON2 SFR. The
UDIS bit affects all Duty Cycle Buffer registers and the
PWM Time Base Period register, PxTPER. No duty
cycle changes or period value changes will have effect
while UDIS = 1.
If the IUE bit is set, any change to the Duty Cycle
registers will be immediately updated regardless of the
UDIS bit state. The PWM Period register (PxTPER)
updates are not affected by the IUE control bit.
14.16 PWM Special Event Trigger
The PWM module has a Special Event Trigger that
allows ADC conversions to be synchronized to the
PWM time base. The ADC sampling and conversion
time can be programmed to occur at any point within
the PWM period. The Special Event Trigger allows the
programmer to minimize the delay between the time
when ADC conversion results are acquired and the
time when the duty cycle value is updated.
DS70283B-page 156
the PWM outputs go to the states defined in the
PxFLTACON registers. The PWM outputs remain
in this state until the Fault pin is driven high and
the corresponding interrupt flag has been cleared
in software. When both of these actions have
occurred, the PWM outputs return to normal oper-
ation at the beginning of the next PWM cycle or
half-cycle boundary. If the interrupt flag is cleared
before the Fault condition ends, the PWM module
waits until the Fault pin is no longer asserted to
restore the outputs.
is driven low, the PWM outputs remain in the
defined Fault states for as long as the Fault pin is
held low. After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle or
half-cycle boundary.
FAULT INPUT MODES
Preliminary
The PWM Special Event Trigger has an SFR named
PxSECMP, and five control bits to control its operation.
The PxTMR value for which a Special Event Trigger
should occur is loaded into the PxSECMP register.
When the PWM time base is in Up/Down Count mode,
an additional control bit is required to specify the count-
ing phase for the Special Event Trigger. The count
phase is selected using the SEVTDIR control bit in the
PxSECMP SFR:
• If the SEVTDIR bit is cleared, the Special Event
• If the SEVTDIR bit is set, the Special Event Trig-
The SEVTDIR control bit has no effect unless the PWM
time base is configured for an Up/Down Count mode.
14.16.1
The PWM Special Event Trigger has a postscaler that
allows a 1:1 to 1:16 postscale ratio. The postscaler is
configured by writing the SEVOPS<3:0> control bits in
the PWMxCON2 SFR.
The special event output postscaler is cleared on the
following events:
• Any write to the PxSECMP register
• Any device Reset
14.17 PWM Operation During CPU Sleep
The Fault A and Fault B input pins can wake the CPU
from Sleep mode. The PWM module generates an
interrupt if either of the Fault pins is driven low while in
Sleep mode.
14.18 PWM Operation During CPU Idle
The PxTCON SFR contains a PTSIDL control bit. This
bit determines if the PWM module will continue to
operate or stop when the device enters Idle mode. If
PTSIDL = 0, the module will continue to operate. If
PTSIDL = 1, the module will stop operation as long as
the CPU remains in Idle mode.
Trigger occurs on the upward counting cycle of
the PWM time base.
ger occurs on the downward count cycle of the
PWM time base.
Mode
Mode
SPECIAL EVENT TRIGGER
POSTSCALER
© 2007 Microchip Technology Inc.