DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 162

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 14-5:
DS70283B-page 160
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
2:
Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in
the FPOR Configuration register.
PWM2 supports only 1 PWM I/O pin pair.
Unimplemented: Read as ‘0’
PMOD4:PMOD1: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
Unimplemented: Read as ‘0’
PEN3H:PEN1H: PWMxH I/O Enable bits
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled, I/O pin becomes general purpose I/O
Unimplemented: Read as ‘0’
PEN3L:PEN1L: PWMxL I/O Enable bits
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled, I/O pin becomes general purpose I/O
PEN3H
R/W-1
U-0
—
PWMxCON1: PWM CONTROL REGISTER 1
(1)
W = Writable bit
‘1’ = Bit is set
PEN2H
R/W-1
U-0
—
(1)
PEN1H
R/W-1
U-0
Preliminary
—
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(2)
PEN3L
PMOD3
R/W-0
R/W-1
(1)
© 2007 Microchip Technology Inc.
x = Bit is unknown
PEN2L
PMOD2
R/W-0
R/W-1
(1)
PEN1L
PMOD1
R/W-0
R/W-1
bit 8
bit 0
(1)