DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 157

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.12.2
If the OSYNC bit in the PWMxCON2 register is set, all
output overrides performed via the PxOVDCON regis-
ter are synchronized to the PWM time base.
Synchronous output overrides occur at the
following times:
• Edge-Aligned mode – When PxTMR is zero
• Center-Aligned modes – When PxTMR is zero
14.13 PWM Output and Polarity Control
Three device Configuration bits are associated with the
PWM module that provide PWM output pin control:
• HPOL Configuration bit
• LPOL Configuration bit
• PWMPIN Configuration bit
These three bits in the FPOR Configuration register
(see Section 20.0 “Special Features”) work in con-
junction with the eight PWM Enable bits (PENxH<4:1>,
PENxL<4:1>) located in the PWMxCON1 SFR. The
Configuration bits and PWM Enable bits ensure that
the PWM pins are in the correct states after a device
Reset occurs.
The PWMPIN configuration fuse allows the PWM mod-
ule outputs to be optionally enabled on a device Reset.
If PWMPIN = 0, the PWM outputs are driven to their
inactive states at Reset. If PWMPIN = 1 (default), the
PWM outputs will be tri-stated. The HPOL bit specifies
the polarity for the PWMxH outputs. The LPOL bit
specifies the polarity for the PWMxL outputs.
14.13.1
The PENxH<4:1> and PENxL<4:1> control bits in the
PWMxCON1 SFR enable each high PWM output pin
and each low PWM output pin, respectively. If a partic-
ular PWM output pin is not enabled, it is treated as a
general purpose I/O pin.
14.14 PWM Fault Pins
There is one Fault pin (FLTAx) associated with the
PWM module. When asserted, this pin can optionally
drive each of the PWM I/O pins to a defined state.
© 2007 Microchip Technology Inc.
and the value of PxTMR matches PxTPER
OVERRIDE SYNCHRONIZATION
OUTPUT PIN CONTROL
Preliminary
14.14.1
The PxFLTACON SFR have four control bits that deter-
mine whether a particular pair of PWM I/O pins is to be
controlled by the Fault input pin. To enable a specific
PWM I/O pin pair for Fault overrides, the corresponding
bit should be set in the PxFLTACON register.
If all enable bits are cleared in the PxFLTACON regis-
ter, the corresponding Fault input pin has no effect on
the PWM module and the pin can be used as a general
purpose interrupt or I/O pin.
14.14.2
The PxFLTACON Special Function Registers have
eight bits each that determine the state of each PWM
I/O pin when it is overridden by a Fault input. When
these bits are cleared, the PWM I/O pin is driven to the
inactive state. If the bit is set, the PWM I/O pin is
driven to the active state. The active and inactive
states are referenced to the polarity defined for each
PWM I/O pin (HPOL and LPOL polarity control bits).
A special case exists when a PWM module I/O pair is
in the Complementary mode and both pins are pro-
grammed to be active on a Fault condition. The
PWMxH pin always has priority in the Complementary
mode, so that both I/O pins cannot be driven active
simultaneously.
14.14.3
If both Fault input pins have been assigned to control a
particular PWM I/O pin, the Fault state programmed for
the Fault A input pin takes priority over the Fault B input
pin.
Note:
FAULT PIN ENABLE BITS
The Fault pin logic can operate indepen-
dent of the PWM logic. If all the enable bits
in the PxFLTACON registers are cleared,
then the Fault pin(s) could be used as gen-
eral purpose interrupt pin(s). Each Fault
pin has an interrupt vector, interrupt flag bit
and interrupt priority bits associated with it.
FAULT STATES
FAULT PIN PRIORITY
DS70283B-page 155