PSB21150FV14NT Infineon Technologies, PSB21150FV14NT Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
PSB21150FV14NT
Manufacturer Part Number
PSB21150FV14NT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21150FV14NT.pdf
(270 pages)
Specifications of PSB21150FV14NT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
- Current page: 4 of 270
- Download datasheet (4Mb)
Table of Contents
1
1.1
1.2
1.3
2
3
3.1
3.2
3.2.1
3.2.1.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.7.1
3.3.7.2
3.3.8
3.3.9
3.3.10
3.3.11
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2
3.5.2.1
Data Sheet
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . . 33
Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parallel Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
S/T-Interface Multiframing
Multiframe Synchronization (M-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . . 57
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
S/T Interface Delay Compensation (TE/LT-T Mode) . . . . . . . . . . . . . . . 65
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . 71
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
State Machine TE and LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
S-Transceiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . 75
States (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
C/I Codes (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Infos on S/T (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4
PSB/PSF 21150
2003-01-30
IPAC-X
Page
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