PSB21150FV14NT Infineon Technologies, PSB21150FV14NT Datasheet - Page 229
PSB21150FV14NT
Manufacturer Part Number
PSB21150FV14NT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21150FV14NT.pdf
(270 pages)
Specifications of PSB21150FV14NT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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MODEB
Note: After an XPR interrupt further data has to be written to the XFIFOB and the
4.6.5
Value after reset: C0
MDS2-0 ... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0
0
0
0
0
1
1
Data Sheet
0
0
1
1
0
1
appropriate Transmit Command (XTF) has to be written to the CMDRB register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAB).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
0 Reserved
1 Reserved
0 Non-Auto
1 Non-Auto
0 Extended
0 Transparent
7
Mode
mode
mode
transparent
mode
mode 0
MDS2 MDS1 MDS0
MODEB - Mode Register
H
Number
of
Address
Bytes
1
2
–
1.Byte
RAL1,RAL2
RAH1,RAH2,
Group Address
–
0
229
Address Comparison
RAC
0
Detailed Register Description
2.Byte
–
RAL1,RAL2,
Group Address
–
0
0
PSB/PSF 21150
0
Remark
One-byte
address
compare.
Two-byte
address
compare.
No address
compare. All
frames
accepted.
2003-01-30
IPAC-X
RD/WR
(72/82)
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