PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 37

• Manufacturer Part Number: PEF82912FV14XP
• Manufacturer: Lantiq

Specifications of PEF82912FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note: For a selected interface mode which does not require all pins (e.g. address pins)
A read/write access to the Q-SMINT I registers can be done in multiplexed or non-
multiplexed mode.
In non-multiplexed mode the register address must be applied to the address bus (A0-
A6) for the data access via the data bus (D0-D7).
In multiplexed mode the address on the address bus (AD0-AD7) is latched in by ALE
before a read/write access via the address/data bus is performed.
The Q-SMINT I provides two different ways to address the register contents which can
be selected with the AMOD bit in the MODE2 register. The address mode after reset is
the indirect address mode (AMOD = ’0’). Reprogramming into the direct address mode
(AMOD = ’1’) has to take place in the indirect address mode.
register addressing modes.
Direct address mode (AMOD = ’1’): The register address to be read or written is directly
set in the way described above.
Indirect address mode (AMOD = ’0’):
• non-muxed: only the LSB of the address bus (A0)
• muxed: only the LSB of the address-data bus (AD0)
gets evaluated to address a virtual ADDRESS (0
Every access to a target register consists of:
• a write access (muxed or non-muxed) to ADDRESS to store the target register´s
• a read access (muxed or non-muxed) from DATA to read from the target register or
• a write access (muxed or non-muxed) to DATA to write to the target register
Data Sheet
address, as well as
the unused pins must be tied to V
DD
.
23
H
) and a virtual DATA (1
Functional Description
Figure 8
PEF 82912/82913
illustrates both
H
) register.
2001-03-30