PEF82912FV14XP Lantiq, PEF82912FV14XP Datasheet - Page 161
PEF82912FV14XP
Manufacturer Part Number
PEF82912FV14XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF82912FV14XP.pdf
(240 pages)
Specifications of PEF82912FV14XP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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4.5
The point of time when mode settings are detected and executed differs with the mode
register type. Two different behaviors can be classified:
• evaluation and execution after SW-reset (C/I= RES) or upon transition out of state
• immediate evaluation and execution
Below the mode registers are listed and grouped according to the different evaluation
times as stated above.
Table 35
Register
Registers Evaluated After SW-Reset or Upon Transition Out of State Deactivated
OPMODE
MFILT
Immediate Evaluation and Execution
OPMODE
M4RMASK
M4WMASK
TEST
LOOP
MASKU
Data Sheet
’Deactivated’
Note: Write access to these registers/bits is allowed only, while the state machine is
in state Reset or Deactivated.
U-Transceiver Mode Register Evaluation Timing
U-Transceiver Mode Register Evaluation Timing
Affected Bits
bit UCI, MLT
complete register
bit FEBE, CI_SEL
complete register
complete register
complete register
complete register
complete register
147
Register Description
PEF 82912/82913
2001-03-30
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