PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 63

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 31
Note: Lower or higher values than 34 k W may be used as well, however for values above
3.3.8
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
3.3.9
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-
bit in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
Data Sheet
34 k W the additional delay must be compensated by setting TR_CONF2.PDS=1
(compensates 260 ns) so the allowed input phase delay is not violated.
S/T Interface Delay Compensation (TE/LT-T mode)
Level Detection Power Down
Note: Capacitors (up to 10 pF) are optional for noise reduction.
SR2
SR1
External Circuitry for Symmetrical Receivers
GND
R1
R1
63
Description of Functional Blocks
R2
R2
V
DD
1:1
21150_33
S Bus
PEB 3086
2003-01-30
ISAC-SX