PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 188

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MASKTR
TR_
MODE
x ... Reserved
Bits set to “1” in this bit position must be ignored.
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the register TR_STA.
SQC ... S/Q-Channel Change
A change in the received S-channel (TE) or Q-channel (NT) has been detected. The new
code can be read from the SQRxx bits of registers SQRR1-3 within the next multiframe
(5 ms). This bit is reset by a read access to the corresponding SQRRx register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the next multiframes (5 ms). This bit is reset by writing register SQXRx.
4.2.13
Value after reset: FF
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.14
Value after reset: 000000xx
Data Sheet
7
7
MASKTR - Mask Transceiver Interrupt
TR_MODE - Transceiver Mode Register 1
1
0
H
1
0
B
0
1
1
0
188
DCH_
INH
LD
MODE
RIC
2
Detailed Register Description
MODE
SQC
1
0
0
MODE
SQW
0
RD/WR (3A)
RD/WR (39)
PEB 3086
2003-01-30
ISAC-SX