PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 145

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

The ISAC-SX indicates to the host that a new data block can be read from the RFIFOx
by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFOx
and information about the received frame is available in the RBCLx and RBCHx registers
and the RSTAx bytes which are listed in
Table 19
Information
Type of frame
(Command/
Response)
Recognition of SAPI
Recognition of TEI
Result of CRC check
(correct/incorrect)
Valid Frame
Abort condition detected
(yes/no)
Data overflow during reception
of a frame (yes/no)
Number of bytes received in
RFIFO
Message length
RFIFO Overflow
The RSTAx register is always appended in the RFIFOx as last byte to the end of a frame.
Note: The number of bytes received in RFIFOx depends on the selected receive FIFO
Data Sheet
threshold (EXMx.RFBS).
Receive Information at RME Interrupt
Register
RSTAx
RSTAD
RSTAB
RSTAD
RSTAB
RSTAx
RSTAx
RSTAx
RSTAx
RBCL
RBCLx
RBCHx
RBCHx
Table
145
Bit
C/R
SA1, 0
HA1, 0
TA
LA
CRC
VFR
RAB
RDO
RBC4-0
RBC11-0 All
OV
19.
Description of Functional Blocks
Mode
Non-auto mode,
2-byte address field
Transparent mode 1
Non-auto mode,
2-byte address field
Transparent mode 1
All except
transparent mode 0
All
All
All
All
All
All
PEB 3086
2003-01-30
ISAC-SX