PEB3086HV14XP Infineon Technologies, PEB3086HV14XP Datasheet - Page 195

• Manufacturer Part Number: PEB3086HV14XP
• Manufacturer: Infineon Technologies

Specifications of PEB3086HV14XP

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

XXX_
TSDPxy
4.4.2
Register
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
BCH_TSDP_BC1
BCH_TSDP_BC2
TR_TSDP_BC1
TR_TSDP_BC2
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA),
B-channel controller (BCH) and Transceiver (TR).
The B-channel controller (BCH) can access any combination of two 8-bit timeslots and
one 2-bit timeslot (e.g. 16-bit access to B1+B2 or 18-bit IDSL in 2B+D). The position of
the two 8-bit timeslots is programmed in BCH_TSDP_BC1 and BCH_TSDP_BC2. The
position of the 2-bit timeslot is programmed in BCH_CR. In the same registers each of
the three timeslots is enabled/disabled.
The position of B-channel data from the S-interface is programmed in TR_TSDP_BC1
and TR_TSDP_BC2.
Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection
Data Sheet
(MODE0/1) and channel selection (CH0-2).
7
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
DPS
Register
Address
44
45
46
47
48
49
4C
4D
0
H
H
H
H
H
H
H
H
0
Value after Reset
00
01
80
81
80
81
00
01
195
H
H
H
H
H
H
H
H
( = output on B1-DD)
( = output on B2-DD)
( = output on B1-DU)
( = output on B2-DU)
( = output on B1-DU)
( = output on B2-DU)
( = transceiver output on B1-DD), see note
( = transceiver output on B2-DD), see note
TSS
Detailed Register Description
0
PEB 3086
2003-01-30
ISAC-SX
RD/WR
(44-4D)