PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 84

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.7.2.2
The strobed IOM-2 bit clock is active during the programmed window. Outside the
programmed window a ’0’ is driven. Two examples are shown in
Figure 46
The strobed bit clock can be enabled in SDS_CONF.SDS_BCL.
3.7.3
The IOM-2 MONITOR channel
MONITOR channel between a master mode device and a slave mode device.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the IOM-2
channels (3 IOM-2 channels in TE mode) can be selected by setting the MONITOR
channel selection bits (MCS) in the MONITOR control register (MON_CR).
Data Sheet
FSC
DD,DU
SDS
(Example1)
SDS
(Example2)
Example 1:
Example 2:
For all examples SDS_CONF.SDS_BCL must be set to “1”.
Strobed IOM-2 Bit Clock
IOM-2 Monitor Channel
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01
Setting of SDS_CR:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
TS0
B1
TS1
B2
MON0
TS2
= '0'
= '0'
= '1'
= '1'
= '1'
= '0'
= '0
= '5
D CI0
H
H
TS3
'
'
(Figure
M
R
M
X
TS4
IC1
47) is utilized for information exchange in the
TS5
IC2 MON1
84
TS6
CI1
TS7
Description of Functional Blocks
M
R
M
X
TS8
TS9
Figure
TS10
TS11
46.
ISAC-SX TE
3186_03.vsd
TS0
PSB 3186
2003-01-30
TS1
H