PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 163

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MSTA
MRC ... MR Bit Control
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
1: MR is internally controlled by the ISAC-SX TE according to MONITOR channel
protocol.
MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC ... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled by the ISAC-SX TE according to MONITOR
channel protocol.
4.3.18
Value after reset: 00
MAC ... MONITOR Transmit Channel Active
The data transmisson in the MONITOR channel is in progress.
TOUT ... Time-Out
Read-back value of the TOUT bit.
Data Sheet
a packet (if MRE = 1).
In addition, the MDR interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE = 1).
MSTA - MONITOR Status Register
0
H
0
0
0
163
0
MAC
Detailed Register Description
0
TOUT
ISAC-SX TE
PSB 3186
2003-01-30
RD (5F)