PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 44

• Manufacturer Part Number: PSB3186FV14NP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3.3.3
In the state F7 (Activated) the B1, B2, D and E bits are transferred transparently from the
S/T to the IOM-2 interface. In all other states ’1’s are transmitted to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary .
the IOM-2 and the S/T interface and vice versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (MODED.DIM0=0). If S/G evaluation is enabled
(MODED.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
Figure 18
Data Sheet
NT -> TE
TE -> NT
FSC
DU
DD
B1
B1
Data Transfer and Delay between IOM-2 and S/T
F
B2 D
B2 D
F
Data Delay between IOM-2 and S/T Interface
B1
B1
E
D
D
B2
E
B2
E
B1
B1
B2 D
D
B2 D
D
B1
B1
E
D
D
B2
B2
E
E
44
B1
B1
D
F
Figure 18
D
B2 D
F
B2 D
B1
B1
E
Description of Functional Blocks
D
D
shows the data delay between
B2
E
B2
E
B1
B1
B2 D
B2 D
D
D
B1
B1
E
D
ISAC-SX TE
D
B2
B2
E
PSB 3186
E
2003-01-30
line_iom_s.vsd
D
D