PSB3186FV14NP Infineon Technologies, PSB3186FV14NP Datasheet - Page 177
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PSB3186FV14NP
Manufacturer Part Number
PSB3186FV14NP
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV14NP.pdf
(200 pages)
Specifications of PSB3186FV14NP
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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5.6
Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below
figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles),
however, the timing parameters are valid both in single and double clock mode.
Figure 72
Parameter
IOM output data delay
IOM input data setup
IOM input data hold
FSC strobe delay (see note)
Strobe signal delay
BCL / FSC delay
Data Sheet
IOM-2 Interface Timing
IOM-2 Timing (TE mode)
Symbol
t
t
t
t
t
t
IOD
IIS
IIH
FSD
SDD
BCD
177
min.
4
3
-135
Limit Values
Electrical Characteristics
max.
60
15
50
30
ISAC-SX TE
PSB 3186
2003-01-30
Unit
ns
ns
ns
ns
ns
ns
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