ICS1893AFI IDT, Integrated Device Technology Inc, ICS1893AFI Datasheet - Page 95
ICS1893AFI
Manufacturer Part Number
ICS1893AFI
Description
PHYCEIVER LOW PWR 3.3V 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheet
1.ICS1893AFT.pdf
(136 pages)
Specifications of ICS1893AFI
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Other names
1893AFI
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8.13.8 Link Loss Inhibit (bit 18.1)
8.13.9 Squelch Inhibit (bit 18.0)
ICS1893AF, Rev. D 10/26/04
The Link Loss Inhibit bit allows an STA to prevent the ICS1893AF from dropping the link in 10Base-T mode.
When an STA sets this bit to logic:
•
•
The Squelch Inhibit bit allows an STA to control the ICS1893AF Squelch Detection in 10Base-T mode.
When an STA sets this bit to logic:
•
•
Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
One, the ICS1893AF 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
Zero, before the ICS1893AF can establish a valid link, the ICS1893AF must receive valid 10Base-T
data.
One, before the ICS1893AF can establish a valid link, the ICS1893AF must receive both valid 10Base-T
data followed by an IDL.
ICS1893AF Data Sheet - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
95
Chapter 8 Management Register Set
October, 2004
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