PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 81

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PIC18F2320-I/SO

Manufacturer Part Number
PIC18F2320-I/SO
Description
Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2320-I/SO

A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
8K Bytes
Ram Size
512 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.
TABLE 6-2:
 2003 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
PROGRAM_MEMORY
Name
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIE
OSCFIP
OSCFIF
EEPGD
Bit 7
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ COUNTER_HI
GOTO
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
CMIP
CMIE
CMIF
Bit 6
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
PROGRAM_LOOP
EECON1,WREN
bit 21
Bit 5
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
FREE
Bit 4
INTE
EEIP
EEIF
EEIE
PIC18F2220/2320/4220/4320
WRERR
BCLIP
BCLIE
BCLIF
RBIE
Bit 3
; disable interrupts
; required sequence
; write 55H
; write AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
TMR0IF
6.6
See Section 23.0 “Special Features of the CPU”
(Section 23.5 “Program Verification and Code Pro-
tection”) for details on code protection of Flash
program memory.
WREN
LVDIP
LVDIE
LVDIF
Bit 2
Flash Program Operation During
Code Protection
TMR3IP
TMR3IF
TMR3IE
INTF
Bit 1
WR
CCP2IP
CCP2IE
CCP2IF
RBIF
Bit 0
RD
--00 0000 --00 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
xx-0 x000 uu-0 u000
11-1 1111 ---1 1111
00-0 0000 ---0 0000
00-0 0000 ---0 0000
POR, BOR
Value on:
DS39599C-page 79
Value on
all other
Resets

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