PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 145

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is an upwardly compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured
CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM Delay register, ECCP1DEL, which is loaded at
either the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets instead of
starting immediately. This means that enhanced PWM
FIGURE 16-1:
 2003 Microchip Technology Inc.
Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base.
CCPR1H (Slave)
Duty Cycle Registers
Enhanced PWM Mode
Comparator
CCPR1L
PR2
TMR2
by
Comparator
setting
(Note 1)
Clear Timer,
set CCP1 pin and
latch D.C.
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
the
P1M1:P1M0
R
S
PIC18F2220/2320/4220/4320
P1M1<1:0>
Q
and
PWM1CON
Controller
Output
2
CCP1/P1A
waveforms do not exactly match the standard PWM
waveforms but are instead offset by one full instruction
cycle (4 T
As before, the user must manually configure the
appropriate TRISD bits for output.
16.4.1
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 15.5 “PWM Mode”. The Half-
Bridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
P1C
P1D
P1B
CCP1M<3:0>
4
OSC
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
PWM OUTPUT CONFIGURATIONS
).
RC2/CCP1/P1A
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
DS39599C-page 143