PIC18F2320-I/SO Microchip Technology Inc., PIC18F2320-I/SO Datasheet - Page 210

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: Microcontroller; 8 KB Flash; 512 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2320-I/SO

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 512 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2220/2320/4220/4320
18.4.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 18-8:
TABLE 18-9:
DS39599C-page 208
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
Name
RC7/RX/DT pin
RC6/TX/CK pin
Note:
Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.
(Interrupt)
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
RXREG
by
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Read
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
PSPIP
CSRC
SPEN
GIEH
Bit 7
GIE/
setting
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
RX9
TX9
either
TMR0IE INT0IE
SREN
enable
bit 0
TXEN
RCIE
RCIP
RCIF
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit,
CREN ADDEN
SYNC
TXIE
TXIP
Bit 4
TXIF
SREN
bit 2
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
bit 3
TMR0IF INT0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
BRGH
FERR
Bit 2
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
OERR
TRMT
Bit 1
bit 5
RX9D
TX9D
RBIF
Bit 0
 2003 Microchip Technology Inc.
bit 6
0000 000x 0000 000u
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
bit 7
Q1 Q2 Q3 Q4
Value on
all other
Resets
‘0’